1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a constant-voltage circuit for supplying a constant voltage to a plurality of constant-current sources, and more particularly, to an arrangement of the constant-voltage circuit and a terminal node of a bus line from which a power source voltage is supplied to the bus line.
2. Description of Related Art
In a bipolar type semiconductor integrated circuit, a plurality of constant-current sources 2 as shown in FIG. 1 are employed, in which an NPN bipolar transistor Q.sub.1 is connected at its emitter to a lower side voltage source 10 (for example, negative voltage V.sub.EE) through a resistor R.sub.1, to an input terminal 9 at its base through a resistor R.sub.2 to receive a constant voltage V.sub.C to control the constant current I.sub.CS, and to a constant-current supplying terminal 8 at its collector for supplying the constant current I.sub.CS to a circuit such as an emitter coupled circuit.
The constant voltage V.sub.C is supplied from an output terminal 12 of a constant-voltage circuit 4 as shown in FIG. 2, which is formed between and connected to a higher side voltage source 11 (for example, positive or ground voltage V.sub.CC) and the lower side voltage source 10, and is constituted of NPN bipolar transistors Q.sub.2 to Q.sub.5 and resistors R.sub.3 to R.sub.8.
In the constant-voltage circuit 4 in FIG. 2, the constant voltage V.sub.C is generated based on the voltage of the lower side voltage source 10, that is, the level of the constant voltage output from the output terminal 12 depends on the voltage level at a portion of the lower side voltage source line 10 to which portion the constant-voltage circuit is connected. On the other hand, in the constant-current source 2 of FIG. 1, the constant current I.sub.CS is generated based on the voltage of the lower side voltage source 10, that is, the level of the constant current I.sub.CS flowing the transistor Q.sub.1 depends on the voltage level at a portion of the lower side voltage source line 10 to which portion the corresponding constant-current source is connected.
Referring to FIG. 3, a conventional semiconductor integrated circuit will be explained. A bus line 31 of the lower side voltage V.sub.EE is formed along a peripheral straight edge line 5 of a semiconductor chip 20, and the voltage V.sub.EE is fed to the bus line 1 from terminal node 3 positioned at both end portions 31" of the bus line 31. Also, constant-voltage circuits 4 are connected to the portions 31" of the bus line 31, respectively, and between the constant-voltage circuits 4 a constant-current source group, in which a plurality of constant-current sources 2 are arranged along the bus line 1, is positioned. The constant-current sources 2 are connected to the corresponding portions of the bus line 31 through lines 22, respectively, and the constant voltage V.sub.C is fed from the output terminals 12 (FIG. 2) of the constant-voltage circuits 4 to the respective input terminals 9 (FIG. 1) of the constant-current sources 2 through a main wiring line 23 and branch wiring lines 24.
Returning to FIG. 1, the value of the constant current I.sub.CS supplied from the terminal 8 is determined by the potential difference between V.sub.C and V.sub.EE, the base emitter forward voltage nature of the transistor Q.sub.1 and the value of the resistor R.sub.1, and base current I.sub.b calculated by I.sub.CS /h, where h is current amplification factor of the transistor Q.sub.1, flows the base of the transistor Q.sub.1 as a load current of the constant-voltage circuit 2.
In FIG. 3, the constant voltage V.sub.C is supplied to a plurality of the constant-current sources 2 through the line 23 and lines 24 from two of the constant-voltage circuits 4, and the value of the constant voltage V.sub.C is deviated at every portion of the main line 23 i.e. at every constant-current source 2 by the voltage drop due to the load current I.sub.b (FIG. 1), as indicated by the characteristic curve 6 of V.sub.C in FIG. 4. Namely, the value of V.sub.C become lower as remoter from the constant-voltage circuits 4, and from the end portions 23" to the middle portion 23' of the wiring 23 the V.sub.C is reduced by .DELTA.V.sub.C.
On the other hand, the level of the lower side voltage V.sub.EE is deviated at every portion of the bus line 31 to which portion the corresponding constant-current source is connected. The deviation of V.sub.EE is caused by the voltage drop due to the constant current I.sub.CS entering into and flowing within the bus line 31, as indicated by the characteristic curve 7 of V.sub.EE in FIG. 4. Namely, the value of V.sub.EE becomes higher as remoter from the terminal nodes 3 positioned at end portions 31" of the bus line 31, and from the end portions 31" to the middle portion 31' of the bus line 31 the V.sub.EE is increased by .DELTA.V.sub.EE.
As mentioned above, in the prior art, at a portion (at one constant-current source) where the V.sub.C rises, the V.sub.EE falls, and vice versa, and the constant current I.sub.CS is determined by the voltage difference between V.sub.C and V.sub.EE when the resistance of the resistor R.sub.1 is constant. Therefore, the value of the constant current I.sub.CS is largely deviated by the position where the constant-current source is formed. For example, when the voltage drop of V.sub.C in the main wiring line 23 is about 10 mV (.DELTA.V.sub.C), and the voltage rise of V.sub.EE in the bus line 31 is about 30 mV (.DELTA.V.sub.EE, the deviation of the maximum voltage difference between V.sub.C and V.sub.EE becomes about 40 mV. Consequently, the deviation of the value of the constant current I.sub.SC due to the position of the constant current source formation becomes about 10% among the plurality of the constant current sources arranged in one direction, when the voltage difference between V.sub.C and V.sub.EE is 1.2 V where both of the voltage drop and the voltage rise by the wiring lines do not exist, and the base-emitter forward voltage of the transistor Q.sub.1 (FIG. 1) is 0.8 V.
In the conventional semiconductor integrated circuit, accordingly, a depression of a margin on logic threshold value is inevitable, and in case a sufficient margin is designed, the operation speed is decreased.